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1 ltc1142/ltc1142l/ltc1142hv s f ea t u re d u escriptio the ltc ? 1142/ltc1142l/ltc1142hv are dual synchro- nous step-down switching regulator controllers featuring automatic burst mode tm operation to maintain high efficien- cies at low output currents. the devices are composed of two separate regulator blocks, each driving a pair of external complementary power mosfets, at switching frequencies up to 250khz, using a constant off-time current mode archi- tecture providing constant ripple current in the inductor. the operating current level for both regulators is user pro- grammable via an external current sense resistor. wide input supply range allows operation from 3.5v* to 18v (20v maximum). constant off-time architecture provides low drop- out regulation limited only by the r ds(on) of the external mosfet and resistance of the inductor and current sense resistor. the ltc1142 series is ideal for applications requiring dual output voltages with high conversion efficiencies over a wide load current range in a small amount of board space. dual high efficiency synchronous step-down switching regulators n dual outputs: 3.3v and 5v or user programmable n ultra-high efficiency: over 95% possible n current mode operation for excellent line and load transient response n high efficiency maintained over 3 decades of output current n low standby current at light loads: 160 m a/output n independent micropower shutdown: i q < 40 m a n wide v in range: 3.5v to 20v n very low dropout operation: 100% duty cycle n synchronous fet switching for high efficiency n available in standard 28-pin ssop n notebook and palmtop computers n battery-operated digital devices n portable instruments n dc power distribution systems u s a o pp l ic at i figure 1. high efficiency dual 3.3v, 5v u a o pp l ic at i ty p i ca l 1000pf + + + 1000pf pdrive 3 sense + 3 sense ? 3 ndrive 3 pgnd3 sgnd3 c t3 i th3 i th5 c t5 sgnd5 pgnd5 ndrive 5 sense ? 5 sense + 5 pdrive 5 v in3 shutdown 3 shutdown 5 v in5 ltc1142hv c t5 390pf 4 3 25 27 13 11 17 18 r c5 1k c c3 3300pf c c5 3300pf c t3 560pf r c3 1k 0.22 m f 2 24 16 10 9 15 14 20 23 1 28 6 v out5 5v/2a c out5 220 m f 10v 2 r sense5 0.05 w p-ch si9430dy l2 50 m h d2 1n5818 n-ch si9410dy 0v = normal >1.5v = shutdown 0.22 m f c in5 22 m f 25v 2 c in3 22 m f 25v 2 p-ch si9430dy n-ch si9410dy d1 1n5818 c out3 220 m f 10v 2 l1 50 m h r sense3 0.05 w v out3 3.3v/2a v in 5.2v to 18v r sense3, r sense5 : sl-c1-1/2-1r050j l1, l2: coiltronics ctx50-2-mp pins 5, 7, 8, 19, 21, 22: nc 1142 f01 note: components optimized for highest efficiency, not minimum board space. + , ltc and lt are registered trademarks of linear technology corporation. burst mode is a trademark of linear technology corporation. *for ltc1142l-adj only.
2 ltc1142/ltc1142l/ltc1142hv a u g w a w u w a r b s o lu t exi t i s input supply voltage (pins 10, 24) ltc1142, ltc1142l-adj ..................... 16v to C 0.3v ltc1142hv, ltc1142hv-adj ............. 20v to C 0.3v continuous output current (pins 6, 9, 20, 23) .... 50ma sense voltages (pins 1, 14, 15, 28).......... 13v to C 0.3v operating ambient temperature range ...... 0 c to 70 c extended commercial temperature range ........................... C 40 c to 85 c junction temperature (note 1) ............................ 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number consult factory for industrial and military grade parts. order part number wu u package / o rder i for atio ltc1142cg ltc1142hvcg ltc1142hvcg-adj ltc1142lcg-adj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 sense + 1 v fb1 shutdown 1 sgnd1 pgnd1 ndrive 1 nc nc pdrive 2 v in2 c t2 int v cc2 i th2 sense 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 g package, 28-lead ssop t jmax = 125 c, q ja = 95 c/w top view LTC1142-ADJ sense 1 i th1 int v cc1 c t1 v in1 pdrive 1 nc nc ndrive 2 pgnd2 sgnd2 shutdown 2 v fb2 sense + 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 g package, 28-lead ssop t jmax = 125 c, q ja = 95 c/w top view ltc1142 sense 3 i th3 int v cc3 c t3 v in3 pdrive 3 nc nc ndrive 5 nc pgnd5 sgnd5 shutdown 5 sense + 5 sense + 3 shutdown 3 sgnd 3 pgnd 3 nc ndrive 3 nc nc pdrive 5 v in5 c t5 int v cc5 i th5 sense 5 e lectr ic al c c hara terist ics t a = 25 c, v 10 = v 24 = 10v, v shutdown = 0v, unless otherwise noted. symbol parameter conditions min typ max units v 2 , v 16 feedback voltage ltc1142hv-adj, ltc1142l-adj : v 10 , v 24 = 9v l 1.21 1.25 1.29 v i 2 , i 16 feedback current ltc1142hv-adj, ltc1142l-adj l 0.2 1 m a v out regulated output voltage ltc1142, ltc1142hv 3.3v output i load = 700ma, v 24 = 9v l 3.23 3.33 3.43 v 5v output i load = 700ma, v 10 = 9v l 4.90 5.05 5.20 v d v out output voltage line regulation v 10, v 24 = 7v to 12v, i load = 50ma C 40 0 40 mv output voltage load regulation figure 1 circuit 3.3v output 5ma < i load < 2a l 40 65 mv 5v output 5ma < i load < 2a l 60 100 mv output ripple (burst mode) i load = 0a 50 mv p-p i 10 , i 24 input dc supply current (note 2) ltc1142 normal mode 4v < v 10 , v 24 < 12v 1.6 2.1 ma sleep mode 4v < v 24 < 12v, 6v < v 10 < 12v 160 230 m a shutdown v sd1 = v sd2 = 2.1v, 4v < v 10 , v 24 < 12v 10 20 m a input dc supply current (note 2) ltc1142hv, ltc1142hv-adj normal mode 4v < v 10 , v 24 < 18v 1.6 2.3 ma sleep mode 4v < v 24 < 18v, 6v < v 10 < 18v 160 250 m a shutdown v sd1 = v sd2 = 2.1v, 4v < v 10 , v 24 < 18v 10 22 m a
3 ltc1142/ltc1142l/ltc1142hv e lectr ic al c c hara terist ics t a = 25 c, v 10 = v 24 = 10v, v shutdown = 0v, unless otherwise noted. C40 c t a 85 c (note 4), v 10 = v 24 = 10v, unless otherwise noted. v 2 , v 16 feedback voltage ltc1142hv-adj only: v 10 , v 24 = 9v 1.21 1.25 1.29 v i 2 , i 16 feedback current ltc1142hv-adj only 0.2 1 m a v out regulated output voltage ltc1142, ltc1142hv 3.3v output i load = 700ma, v 24 = 9v 3.17 3.33 3.40 v 5v output i load = 700ma, v 10 = 9v 4.85 5.05 5.20 v i 10 , i 24 input dc supply current (note 2) ltc1142 normal mode 4v < v 10 , v 24 < 12v 1.6 2.4 ma sleep mode 4v < v 24 < 12v, 6v < v 10 < 12v 160 260 m a shutdown v shutdown = 2.1v, 4v < v 10 , v 24 < 12v 10 22 m a input dc supply current (note 2) ltc1142hv-adj, ltc1142hv normal mode 4v < v 10 , v 24 < 18v 1.6 2.6 ma sleep mode 4v < v 24 < 18v, 6v < v 10 < 18v 160 280 m a shutdown v shutdown = 2.1v, 4v < v 10 , v 24 < 12v 10 24 m a input dc supply current (note 2) ltc1142l-adj (note 5) normal mode 3.5v < v 10 , v 24 < 12v 1.6 2.4 ma sleep mode 3.5v < v 10 , v 24 < 12v 160 260 m a shutdown v sd1 = v sd2 = 2.1v, 3.5v < v 10 , v 24 < 12v 10 22 m a v 1 C v 28 current sense threshold voltage ltc1142hv-adj, ltc1142l-adj v 15 C v 14 v 14 = v 28 = v out + 100mv, v 2 = v 16 = v ref + 25mv 25 mv v 14 = v 28 = v out C 100mv, v 2 = v 16 = v ref C 25mv 130 150 170 mv ltc1142, ltc1142hv v 28 = v out + 100mv (forced) 25 mv v 28 = v out C 100mv (forced) 125 150 175 mv ltc1142, ltc1142hv v 14 = v out + 100mv (forced) 25 mv v 14 = v out C 100mv (forced) 125 150 175 mv v shutdown shutdown pin threshold 0.55 0.8 2 v t off off-time (note 3) c t = 390pf, i load = 700ma 3.8 5 6 m s symbol parameter conditions min typ max units input dc supply current (note 2) ltc1142l-adj (note 5) normal mode 3.5v < v 10 , v 24 < 12v 1.6 2.1 ma sleep mode 3.5v < v 10 , v 24 < 12v 160 230 m a shutdown v sd1 = v sd2 = 2.1v, 3.5v < v 10 , v 24 < 12v 10 20 m a v 1 C v 28 current sense threshold voltage ltc1142hv-adj, ltc1142l-adj v 15 C v 14 v 14 = v 28 = v out + 100mv, v 2 = v 16 = v ref + 25mv 25 mv v 14 = v 28 = v out C 100mv, v 2 = v 16 = v ref C 25mv l 130 150 170 mv ltc1142, ltc1142hv v 28 = v out + 100mv (forced) 25 mv v 28 = v out C 100mv (forced) l 130 150 170 mv ltc1142, ltc1142hv v 14 = v out + 100mv (forced) 25 mv v 14 = v out C 100mv (forced) l 130 150 170 mv v shutdown shutdown pin threshold 0.5 0.8 2 v i shutdown shutdown pin input current 0v < v shutdown < 8v, v 10 , v 24 = 16v 1.2 5 m a i 11 , i 24 c t pin discharge current v out in regulation, v sense C = v out 50 70 90 m a v out = 0v 2 10 m a t off off-time (note 3) c t = 390pf, i load = 700ma 4 5 6 m s t r , t f driver output transition times c l = 3000pf (pins 6, 9, 20, 23), v 10 , v 24 = 6v 100 200 ns
4 ltc1142/ltc1142l/ltc1142hv e lectr ic al c c hara terist ics the l denotes specifications which apply over the full operating temperature range. note 1: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc1142cg: t j = t a + (p d 95 c/w) note 2: this current is for one regulator block. total supply current is the sum of pins 10 and 24 currents. dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see the applications information section. note 3: in applications where r sense is placed at ground potential, the off- time increases approximately 40%. note 4: the ltc1142/ltc1142hv-adj/ltc1142hv/ltc1142l-adj are not tested and quality-assurance sampled at C 40 c to 85 c. these specifications are guaranteed by design and/or correlation. note 5: the ltc1142l-adj allows operation down to v in = 3.5v. cc hara terist ics uw a t y p i ca lper f o r c e 5v output efficiency load current (a) 0.01 efficiency (%) 100 95 90 85 0.1 1 1142 g01 2 v in = 6v v in = 10v 3.3v output efficiency load current (a) 0.01 efficiency (%) 100 95 90 85 0.1 1 1142 g02 2 v in = 5v v in = 10v 5v efficiency vs input voltage input voltage (v) 0 efficiency (%) 100 98 96 94 92 90 88 86 84 82 80 16 1142 g03 4 8 12 20 figure 1 circuit v out = 5v i load = 1a i load = 100ma 3.3v efficiency vs input voltage load regulation load current (a) 0 d v out (mv) 20 0 20 40 60 80 100 2.0 1142 g06 0.5 1.0 1.5 2.5 figure 1 circuit r sense = 0.05 w v in = 6v v in = 6v v in = 12v v out = 5v v out = 3.3v v in = 12v input voltage (v) 0 d v out (mv) 40 30 20 10 0 10 20 30 ?0 16 1142 g05 4 8 12 20 figure 1 circuit i load = 1a line regulation input voltage (v) 0 efficiency (%) 100 98 96 94 92 90 88 86 84 82 80 16 1142 g04 4 8 12 20 figure 1 circuit v out = 3.3v i load = 1a i load = 100ma
5 ltc1142/ltc1142l/ltc1142hv cc hara terist ics uw a t y p i ca lper f o r c e input voltage (v) 0 supply current (ma) 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 2 10 14 1142 g07 8 18 4 6 12 16 per regulator block not including gate charge current pins 10, 24 active mode sleep mode input voltage (v) 0 supply current ( m a) 20 18 16 14 12 10 8 6 4 2 0 2 10 14 1142 g08 8 18 4 6 12 16 per regulator block pins 10, 24 v shutdown = 2v v in ?v out voltage (v) 0 normalized frequency 12 1142 g09 2 68 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 4 10 70? 0? 25? v out = 5v operating frequency (khz) 20 gate charge current (ma) 140 28 24 20 16 12 8 4 0 1142 g10 80 260 200 q n + q p = 100nc q n + q p = 50nc output voltage (v) 0 off-time ( m s) 80 70 60 50 40 30 20 10 0 4 1142 g11 1 2 3 5 v sense = v out v out = 5v v out = 3.3v pi fu ctio s u uu operating frequency vs v in C v out temperature (?) 0 sense voltage (mv) 175 150 125 100 75 50 25 0 80 1142 g12 20 40 60 100 maximum threshold minimum threshold current sense threshold voltage supply current in shutdown off-time vs output voltage dc supply current gate charge supply current ltc1142/ltc1142hv sense + 3 (pin 1): the (+) input to the 3.3v section current comparator. a built-in offset between pins 1 and 28 in conjunction with r sense3 sets the current trip threshold for the 3.3v section. shutdown 3 (pin 2): when grounded, the 3.3v section operates normally. pulling pin 2 high holds both mosfets off and puts the 3.3v section in micropower shutdown mode. requires cmos logic-level signal with t r , t f < 1 m s. do not float pin 2. sgnd3 (pin 3): the 3.3v section small-signal ground must be routed separately from other grounds to the (C) terminal of the 3.3v section output capacitor. pgnd3 (pin 4): the 3.3v section driver power ground connects to source of n-channel mosfet and the (C) terminal of the 3.3v section input capacitor. nc (pin 5): no connection. ndrive 3 (pin 6): high current drive for bottom n-channel mosfet, 3.3v section. voltage swing at pin 6 is from ground to v in3 .
6 ltc1142/ltc1142l/ltc1142hv nc (pins 7, 8): no connection. pdrive 5 (pin 9): high current drive for top p-channel mosfet, 5v section. voltage swing at this pin is from v in5 to ground. v in5 (pin 10): supply pin, 5v section, must be closely decoupled to 5v power ground pin 18. c t5 (pin 11): external capacitor c t5 from pin 11 to ground sets the operating frequency for the 5v section. (the actual frequency is also dependent upon the input voltage.) int v cc5 (pin 12) : internal supply voltage for the 5v section, nominally 3.3v, can be decoupled to signal ground, pin 17. do not externally load this pin. i th5 (pin 13): gain amplifier decoupling point, 5v sec- tion. the 5v section current comparator threshold in- creases with the pin 13 voltage. sense C 5 (pin 14): connects to internal resistive divider which sets the output voltage for the 5v section. pin 14 is also the (C) input for the current comparator on the 5v section. sense + 5 (pin 15): the (+) input to the 5v section current comparator. a built-in offset between pins 15 and 14 in conjunction with r sense5 sets the current trip threshold for the 5v section. shutdown 5 (pin 16): when grounded, the 5v section operates normally. pulling pin 16 high holds both mosfets off and puts the 5v section in micropower shutdown mode. requires cmos logic signal with t r , t f < 1 m s. do not float pin 16. sgnd5 (pin 17): the 5v section small-signal ground must be routed separately from other grounds to the (C) termi- nal of the 5v section output capacitor. pgnd5 (pin 18): the 5v section driver power ground connects to source of n-channel mosfet and the (C) terminal of the 5v section input capacitor. nc (pin 19): no connection. ndrive 5 (pin 20): high current drive for bottom n-channel mosfet, 5v section. voltage swing at pin 20 is from ground to v in5 . nc (pins 21, 22): no connection. pi fu ctio s u uu pdrive 3 (pin 23): high current drive for top p-channel mosfet, 3.3v section. voltage swing at this pin is from v in3 to ground. v in3 (pin 24): supply pin, 3.3v section, must be closely decoupled to 3.3v power ground, pin 4. c t3 (pin 25): external capacitor c t3 from pin 25 to ground sets the operating frequency for the 3.3v section. (the actual frequency is also dependent upon the input voltage.) int v cc3 (pin 26): internal supply voltage for the 3.3v section, nominally 3.3v, can be decoupled to signal ground, pin 3. do not externally load this pin. i th3 (pin 27): gain amplifier decoupling point, 3.3v section. the 3.3v section current comparator threshold increases with the pin 27 voltage. sense C 3 (pin 28): connects to internal resistive divider which sets the output voltage for the 3.3v section. pin 28 is also the (C) input for the current comparator on the 3.3v section. ltc1142hv-adj/ltc1142l-adj sense + 1 (pin 1): the (+) input to the section 1 current comparator. a built-in offset between pins 1 and 28 in conjunction with r sense1 sets the current trip threshold for this section. v fb1 (pin 2): this pin serves as the feedback pin from an external resistive divider used to set the output voltage for section 1. shutdown 1 (pin 3): when grounded, the section 1 regulator operates normally. pulling pin 3 high holds both mosfets off and puts this section in micropower shut- down mode. requires cmos logic signal with t r , t f < 1 m s. do not float pin 3. sgnd1 (pin 4): the section 1 small-signal ground must be routed separately from other grounds to the (C) termi- nal of the section 1 output capacitor. pgnd1 (pin 5): the section 1 driver power ground con- nects to source of n-channel mosfet and the (C) terminal of the section 1 input capacitor.
7 ltc1142/ltc1142l/ltc1142hv pi fu ctio s u uu ndrive 1 (pin 6): high current drive for bottom n-channel mosfet, section 1. voltage swing at pin 6 is from ground to v in1 . nc (pins 7, 8): no connection. pdrive 2 (pin 9): high current drive for top p-channel mosfet, section 2. voltage swing at this pin is from v in2 to ground. v in2 (pin 10): supply pin, section 2, must be closely decoupled to section 2 power ground, pin 19. c t2 (pin 11): external capacitor c t2 from pin 11 to ground sets the operating frequency for the section 2. (the actual frequency is also dependent upon the input voltage.) int v cc2 (pin 12) : internal supply voltage for section 2, nominally 3.3v, can be decoupled to signal ground, pin 18. do not externally load this pin. i th2 (pin 13): gain amplifier decoupling point, section 2. the section 2 current comparator threshold increases with the pin 13 voltage. sense C 2 (pin 14): connects (C) input for the current comparator on section 2. sense + 2 (pin 15): the (+) input to the section 2 current comparator. a built-in offset between pins 15 and 14 in conjunction with r sense2 sets the current trip threshold for this section. v fb2 (pin 16): this pin serves as the feedback pin from an external resistive divider used to set the output voltage for section 2. shutdown 2 (pin 17): when grounded, the section 2 regulator operates normally. pulling pin 17 high holds both mosfets off and puts section 2 in micropower shutdown mode. requires cmos logic signal with t r , t f < 1 m s. do not float pin 17. sgnd2 (pin 18): the section 2 small-signal ground must be routed separately from other grounds to the (C) termi- nal of the section 2 output capacitor. pgnd2 (pin 19): the section 2 driver power ground connects to source of the n-channel mosfet and the (C ) terminal of the section 2 input capacitor. ndrive 2 (pin 20): high current drive for bottom n- channel mosfet, section 2. voltage swing at pin 20 is from ground to v in2 . nc (pins 21, 22): no connection. pdrive 1 (pin 23): high current drive for top p-channel mosfet, section 1. voltage swing at this pin is from v in1 to ground. v in1 (pin 24): supply pin, section 1. must be closely decoupled to section 1 power ground pin 5. c t1 (pin 25): external capacitor c t1 from pin 25 to ground sets the operating frequency for section 1. (the actual frequency is also dependent upon the input voltage.) int v cc1 (pin 26): internal supply voltage for section 1, nominally 3.3v, can be decoupled to signal ground, pin 4. do not externally load this pin. i th1 (pin 27): gain amplifier decoupling point, section 1. the section 1 current comparator threshold increases with the pin 27 voltage. sense C 1 (pin 28): connects to the (C) input for the current comparator on section 1.
8 ltc1142/ltc1142l/ltc1142hv fu ctio al diagra u uw operatio u the ltc1142 series consists of two individual regulator blocks, each using current mode, constant off-time archi- tectures to synchronously switch an external pair of complementary power mosfets. the two regulators are internally set to provide output voltages of 3.3v and 5v for the ltc1142. the ltc1142hv-adj/ltc1142l-adj are configured to provide two user selectable output voltages, each set by external resistor dividers. operating fre- quency is individually set on each section by the external capacitors at c t , pins 11 and 25. the output voltage is sensed by an internal voltage divider connected to sense C , pin 28 (14) (ltc1142) or external divider returned to v fb , pin 2 (16) (LTC1142-ADJ). a voltage comparator v and a gain block g compare the divided output voltage with a reference voltage of 1.25v. to optimize efficiency, the ltc1142 series automatically switches between two modes of operation, burst mode and continuous mode. the voltage comparator is the primary control element when the device is in burst mode operation, while the gain block controls the output voltage in continuous mode. during the switch on cycle in continuous mode, current comparator c monitors the voltage between pins 1 (15) and 28 (14) connected across an external shunt in series with the inductor. when the voltage across the shunt reaches its threshold value, the pdrive output is switched to v in , turning off the p-channel mosfet. the timing capacitor connected to pin 25 (11) is now allowed to discharge at a rate determined by the off-time controller. the discharge current is made proportional to the output voltage [measured by pin 28 (14)] to model the inductor current, which decays at a rate that is also proportional to the output voltage. while the timing capacitor is discharg- ing, the ndrive output goes to v in , turning on the n-channel mosfet. when the voltage on the timing capacitor has discharged past v th1 , comparator t trips, setting the flip-flop. this causes the ndrive output to go low (turning off the n-channel mosfet) and the pdrive output to also go low (turning the p-channel mosfet back on). the cycle then repeats. refer to functional diagram only one regulator block shown. pin numbers are for 3.3v (5v) sections for ltc1142/ltc1142hv, and v out1 (v out2 ) for ltc1142l-adj/ltc1142hv-adj. + + reference 24(10) 23(9) 6(20) 4(18) 2(16) pgnd ndrive pdrive v in + v + c 25mv to 150mv + 1(15) v os 26(12) 2(16) shutdown int v cc 1.25v 5pf g 27(13) i th q r s v in sense off-time control 25(11) 13k + s sleep v th1 c t t sense + v th2 pin numbers for ltc1142, ltc1142hv pin numbers for ltc1142l-adj ltc1142hv-adj LTC1142-ADJ 3(17) ltc1142l-adj ltc1142hv-adj 4(18) ltc1142l-adj ltc1142hv-adj 2(16) ltc1142l-adj, ltc1142hv-adj: 5(19) ltc1142l-adj ltc1142hv-adj 3(17) 3(17) sgnd 100k 28(14) sense 1142 bd nc/adj
9 ltc1142/ltc1142l/ltc1142hv operatio u refer to functional diagram as the load current increases, the output voltage de- creases slightly. this causes the output of the gain stage [pin 27(13)] to increase the current comparator thresh- old, thus tracking the load current. the sequence of events for burst mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. when the output voltage is at or above the desired regulated value, the p-channel mosfet is held off by comparator v and the timing capacitor continues to discharge below v th1 . when the timing capacitor discharges past v th2 , voltage compara- tor s trips, causing the internal sleep line to go low and the n-channel mosfet to turn off. the circuit now enters sleep mode with both power mosfets turned off. in sleep mode a majority of the circuitry is turned off, dropping the quiescent current from 1.6ma to 160 m a (for one regulator block). the load current is now being supplied from the output capacitor. when the output voltage has dropped by the amount of hysteresis in comparator v, the p-channel mosfet is again turned on and this process repeats. to avoid the operation of the current loop interfering with burst mode operation, a built-in offset v os is incorporated in the gain stage. this prevents the current comparator threshold from increasing until the output voltage has dropped below a minimum threshold. to prevent both the external mosfets from ever being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. before the ndrive output can go high, the pdrive output must also be high. likewise, the pdrive output is prevented from going low while the ndrive output is high. using constant off-time architecture, the operating fre- quency is a function of the input voltage. to minimize the frequency variation as dropout is approached, the off-time controller increases the discharge current as v in drops below v out + 1.5v. in dropout the p-channel mosfet is turned on continuously (100% duty cycle) providing low dropout operation with v out ~ v in . t he basic ltc1142 application circuit is shown in figure 1. external component selection is driven by the load requirement and begins with the selection of r sense . once r sense is known, c t and l can be chosen. next, the power mosfets and d1 are selected. finally, c in and c out are selected and the loop is compensated. since the 3.3v and 5v sections in the ltc1142 are identical and similarly section 1 and section 2 in the ltc1142hv-adj/ ltc1142l-adj are identical, the process of component selection is the same for both sections. the circuit shown in figure 1 can be configured for operation up to an input voltage of 20v. r sense selection for output current r sense is chosen based on the required output current. the ltc1142 current comparators have a threshold range which extends from a minimum of 25mv/r sense to a maximum of 150mv/r sense . the current comparator threshold sets the peak of the inductor ripple current, applicatio s i for atio w uu u yielding a maximum output current i max equal to the peak value less half the peak-to-peak ripple current. for proper burst mode operation, i ripple(p-p) must be less than or equal to the minimum current comparator threshold. since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., i ripple(p-p) = 25mv/r sense (see c t and l selection for operating frequency section). solving for r sense and allowing a margin for variations in the ltc1142 and external component values yields: r sense max = 100mv i a graph for selecting r sense vs maximum output current is given in figure 2. the load current below which burst mode operation com- mences, i burst , and the peak short-circuit current i sc(pk) ,
10 ltc1142/ltc1142l/ltc1142hv applicatio s i for atio w uu u a graph for selecting c t versus frequency including the effects of input voltage is given in figure 3. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations section). the complete expression for operating frequency of the circuit in figure 1 is given by: f t v v off out in =- ? ? ? ? 1 1 where: tc v v off t reg out = ? ? ? ? 13 10 4 . v reg is the desired output voltage (i.e., 5v, 3.3v). v out is the measured output voltage. thus v reg /v out = 1 in regulation. note that as v in decreases, the frequency decreases. when the input-to-output voltage differential drops below 1.5v for a particular section, the ltc1142 reduces t off in that section by increasing the discharge current in c t . this prevents audible operation prior to dropout. figure 2. selecting r sense maximum output current (a) 0 r sense ( w ) 0.20 0.15 0.10 0.05 0 4 1142 f02 1 2 3 5 l and c t selection for operating frequency each regulator section of the ltc1142 uses a constant off- time architecture with t off determined by an external timing capacitor c t . each time the p-channel mosfet switch turns on, the voltage on c t is reset to approximately 3.3v. during the off-time, c t is discharged by a current which is proportional to v out . the voltage on c t is analogous to the current in inductor l, which likewise decays at a rate proportional to v out . thus the inductor value must track the timing capacitor value. the value of c t is calculated from the desired continuous mode operating frequency: c f t = 1 26 10 4 . assumes v in = 2v out , figure 1 circuit. figure 3. timing capacitor value frequency (khz) 0 capacitance (pf) 50 100 150 200 1142 f03 250 1000 800 600 400 200 0 300 v in = 12v v in = 10v v in = 7v v sense = v out = 5v once the frequency has been set by c t , the inductor l must be chosen to provide no more than 25mv/r sense of peak- to-peak inductor ripple current. this results in a minimum required inductor value of: l min = 5.1 10 5 r sense c t v reg as the inductor value is increased from the minimum value, the esr requirements for the output capacitor are both track i max . once r sense has been chosen, i burst and i sc(pk) can be predicted from the following: i burst sense sc(pk) sense 15mv r i= 150mv r ? the ltc1142 automatically extends t off during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. the resulting ripple current causes the average short-circuit current i sc(avg) to be reduced to approximately i max .
11 ltc1142/ltc1142l/ltc1142hv applicatio s i for atio w uu u eased at the expense of efficiency. if too small an inductor is used, the inductor current will decrease past zero and change polarity. a consequence of this is that the ltc1142 may not enter burst mode operation and efficiency will be severely degraded at low currents. inductor core selection once the minimum value for l is known, the type of inductor must be selected. the highest efficiency will be obtained using ferrite, molypermalloy (mpp), or kool m m ? cores. lower cost powdered iron cores provide suitable performance, but cut efficiency by 3% to 7%. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as induc- tance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design cur- rent is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple which can cause burst mode operation to be falsely triggered. do not allow the core to saturate! kool m m (from magnetics, inc.) is a very good, low loss core material for toroids with a soft saturation charac- teristic. molypermalloy is slightly more efficient at high (>200khz) switching frequencies, but it is quite a bit more expensive. toroids are very space efficient, especially when you can use several layers of wire. because they generally lack a bobbin, mounting is more difficult. how- ever, new designs for surface mount are available from coiltronics and beckman industrial corporation which do not increase the height significantly. power mosfet and d1, d2 selection two external power mosfets must be selected for use with each section of the ltc1142: a p-channel mosfet for the main switch, and an n-channel mosfet for the synchronous switch. the main selection criteria for the power mosfets are the threshold voltage v gs(th) and on- resistance r ds(on) . kool m m is a registered trademark of magnetics, inc. the minimum input voltage determines whether standard threshold or logic-level threshold mosfets must be used. for v in > 8v, standard threshold mosfets ( v gs(th) < 4v) may be used. if v in is expected to drop below 8v, logic-level threshold mosfets (v gs(th) < 2.5v) are strongly recommended. when logic-level mosfets are used, the ltc1142 supply voltage must be less than the absolute maximum v gs ratings for the mosfets. the maximum output current i max determines the r ds(on) requirement for the two mosfets. when the ltc1142 is operating in continuous mode, the simplifying assump- tion can be made that one of the two mosfets is always conducting the average load current. the duty cycles for the two mosfets are given by: p-ch duty cycle = v v n-ch duty cycle = vv v out in in out in - from the duty cycles the required r ds(on) for each mosfet can be derived: p-ch r = v v n-ch r = v ds(on) in out ds(on) in + () - () + () p i p vv i p max p n in out max n 2 2 1 1 d d where p p and p n are the allowable power dissipations and d p and d n are the temperature dependencies of r ds(on) . p p and p n will be determined by efficiency and/or thermal requirements (see efficiency considerations). (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.007/ c can be used as an approximation for low voltage mosfets. the schottky diodes d1 and d2 shown in figure 1 only conduct during the dead-time between the conduction of the respective power mosfets. the sole purpose of d1 and d2 is to prevent the body diode of the n-channel mosfet from turning on and storing charge during the
12 ltc1142/ltc1142l/ltc1142hv applicatio s i for atio w uu u dead-time, which could cost as much as 1% in efficiency (although there are no other harmful effects if d1 and d2 are omitted). therefore, d1 and d2 should be selected for a forward voltage of less than 0.6v when conducting i max . c in and c out selection in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capaci- tor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ci vvv v in max out in out in required i rms ? - () [] 12 / this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case conditon is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. an additional 0.1 m f to 1 m f ceramic capacitor is also required on each v in line (pins 10 and 24) for high frequency decoupling. the selection of c out is driven by the required effective series resistance (esr). the esr of c out must be less than twice the value of r sense for proper operation of the ltc1142: c out required esr < 2r sense optimum efficiency is obtained by making the esr equal to r sense . as the esr is increased up to 2r sense , the efficiency degrades by less than 1%. if the esr is greater than 2r sense , the voltage ripple on the output capacitor will prematurely trigger burst mode operation, resulting in disruption of continuous mode and an efficiency hit which can be several percent. manufacturers such as nichicon and united chemicon should be considered for high performance capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr/size ratio of any alumi- num electrolytic at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. in surface mount applications multiple capacitors may have to be parallel to meet the capacitance, esr or rms current handling requirements of the application. alumi- num electrolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. for example, if 200 m f/10v is called for in an application requiring 3mm height, two avx 100 m f/10v (p/n tpsd 107k010) could be used. consult the manufacturer for other specific recommendations. at low supply voltages, a minimum capacitance at c out is needed to prevent an abnormal low frequency operating mode (see figure 4). when c out is made too small, the output ripple at low frequencies will be large enough to trip the voltage comparator. this causes burst mode operation to be activated when the ltc1142 would nor- mally be in continuous operation. the output remains in regulation at all times. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load v in ?v out voltage (v) 0 output capacitance ( m f) 1000 800 600 400 200 0 4 1142 f04 1 2 3 5 l = 50 m h r sense = 0.02 w l = 25 m h r sense = 0.02 w l = 50 m h r sense = 0.05 w figure 4. minimum value of c out
13 ltc1142/ltc1142l/ltc1142hv applicatio s i for atio w uu u current. when a load step occurs, v out shifts by an amount equal to d i load esr, where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out until the regulator loop adapts to the current change and returns v out to its steady- state value. during this recovery time v out can be monitored for overshoot or ringing which would indicate a stability problem. the pin 27 (13) external components shown in the figure 1 circuit will prove adequate com- pensation for most applications. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 c load . thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percent- age of input power. (for high efficiency circuits only small errors are incurred by expressing losses as a percentage of output power.) although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in ltc1142 circuits: 1. ltc1142 dc bias current 2. mosfet gate charge current 3. i 2 r losses 1. the dc supply current is the current which flows into v in (pin 24 for the 3.3v section, pin 10 for the 5v section) less the gate charge current. for v in = 10v the ltc1142 dc supply current for each section is 160 m a with no load, and increases proportionally with load up to a constant 1.6ma after the ltc1142 has entered continuous mode. because the dc bias current is drawn from v in , the resulting loss increases with input voltage. for v in = 10v the dc bias losses are generally less than 1% for load currents over 30ma. however, at very low load currents the dc bias current accounts for nearly all of the loss. 2. mosfet gate charge current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in which is typically much larger than the dc supply current. in continuous mode, i gate(chg) = f (q n + q p ). the typical gate charge for a 0.1 w n-channel power mosfet is 25nc, and for a p-channel about twice that value. this results in i gate(chg) = 7.5ma in 100khz continuous operation, for a 2% to 3% typical mid-current loss with v in = 10v. note that the gate charge loss increases directly with both input voltage and operating frequency. this is the principal reason why the highest efficiency circuits operate at moderate frequencies. furthermore, it ar- gues against using larger mosfets than necessary to control i 2 r losses, since overkill can cost efficiency as well as money! 3. i 2 r losses are easily predicted from the dc resistances of the mosfet, inductor, and current shunt. in continu- ous mode the average output current flows through l and r sense , but is chopped between the p-channel and n-channel mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resis- tances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 0.1 w , r l = 0.15 w , and r sense = 0.05 w , then the total resistance is 0.3 w . this results in losses ranging from 3% to 12% as the output current increases from 0.5a to 2a. i 2 r losses cause the efficiency to roll off at high output currents.
14 ltc1142/ltc1142l/ltc1142hv applicatio s i for atio w uu u figure 5 shows how the efficiency losses in one section of a typical ltc1142 regulator end up being apportioned. the gate charge loss is responsible for the majority of the efficiency lost in the mid-current region. if burst mode operation was not employed at low currents, the gate charge loss alone would cause efficiency to drop to unacceptable levels. with burst mode operation, the dc supply current represents the lone (and unavoidable) loss component which continues to become a higher percent- age as output current is reduced. as expected, the i 2 r losses dominate at high load currents. other losses including c in and c out esr dissipative losses, mosfet switching losses, schottky conduction losses during dead-time and inductor core losses, gener- ally account for less than 2% total additional loss. figure 5. efficiency loss output current (a) 0.01 efficiency/loss (%) 90 95 1 1142 f05 85 80 0.03 0.1 0.3 3 100 gate charge 1/2 ltc1142 i q i 2 r design example as a design example, assume v in = 12v (nominal), 5v section, i max = 2a and f = 200khz; r sense , c t and l can immediately be calculated: r sense = 100mv/2 = 0.05 w t off = (1/200khz) [1 C (5/12)] = 2.92 m s c t5 = 2.92 m s/(1.3 10 4 ) = 220pf l2 min = 5.1 10 5 0.05 w 220pf 5v = 28 m h assume that the mosfet dissipations are to be limited to p n = p p = 250mw. if t a = 50 c and the thermal resistance of each mosfet is 50 c/ w, then the junction temperatures will be 63 c and d p = d n = 0.007(63 C 25) = 0.27. the required r ds(on) for each mosfet can now be calculated: pch - r n - ch r ds(on) ds(on) == == 12 0 25 52 127 012 12 0 25 52 127 0 085 2 2 (. ) ()(. ) . (. ) ()(. ) . w w the p-channel requirement can be met by a si9430dy, while the n-channel requirement is exceeded by a si9410dy. note that the most stringent requirement for the n-channel mosfet is with v out = 0 (i.e., short circuit). during a continuous short circuit, the worst case n-channel dissipation rises to: p n = i sc(avg) 2 r ds(on) (1 + d n ) with the 0.05 w sense resistor, i sc(avg) = 2a will result, increasing the 0.085 w n-channel dissipation to 450mw at a die temperature of 73 c. c in will require an rms current rating of at least 1a at temperature, and c out will require an esr of 0.05 w for optimum efficiency. now allow v in to drop to its minimum value. at lower input voltages the operating frequency will decrease and the p-channel will be conducting most of the time, causing its power dissipation to increase. at v in(min) = 7v: f min = (1/2.92 m s)[1 C (5v/ 7v)] = 98khz p va v mv p == 5 0 12 2 1 27 7 435 2 (. )( )(. ) w a similar calculation for the 3.3v section results in the component values shown in figure 14. ltc1142hv-adj/ltc1142l-adj adjustable applications when an output voltage other than 3.3v or 5v is required, the ltc1142 adjustable version is used with an external resistive divider from v out to v fb , pin 2 (16). the regu- lated output voltage is determined by: v r r out =+ ? ? ? ? 125 1 2 1 .
15 ltc1142/ltc1142l/ltc1142hv applicatio s i for atio w uu u to prevent stray pickup a 100pf capacitor is suggested across r1 located close to the ltc1142hv-adj/ltc1142l- adj as in figure 6. the external divider network must be placed across c out with the negative plate of c out returned to signal ground. refer to the board layout checklist. figure 6. LTC1142-ADJ external feedback network board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1142. these items are also illustrated graphically in the layout diagram of figure 7. in general each block should be self-contained with little cross coupling for best performance. check the following in your layout: 1. are the signal and power grounds segregated? the ltc1142 signal ground [pin 3 (17) for the ltc1142, pin 4 (18) for LTC1142-ADJ] must return to the (C) plate of c out . the power ground returns to the source of the n-channel mosfet, anode of the schottky diode, and (C) plate of c in , which should have as short lead lengths as possible. 2. does the ltc1142 sense C , pin 28 (14) connect to a point close to r sense and the (+) plate of c out ? 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the 1000pf capacitor r sense 100pf r2 r1 + c out v out v fb [pin 2(16)] sgnd [pin 4(18)] 1142 f06 + 1000pf 28 27 26 25 24 23 22 21 20 19 18 17 16 15 sense 3 i th3 int v cc3 c t3 v in3 ndrive 5 pgnd5 sgnd5 shutdown 5 sense + 5 ltc1142 1 2 3 4 5 6 7 8 9 10 11 12 13 14 + + pdrive 3 nc nc pdrive 5 nc nc nc v in3 nc v in5 1000pf 3300pf 3300pf 1k 1k c t5 + c out3 r sense3 + v out3 + v in3 c in3 l1 n-ch p-ch 1 m f 1 m f p-ch n-ch c in5 d1 d2 l2 + c out5 + + v in5 r sense5 v out5 1142 f07 shutdown (5v output) sgnd3 shutdown (3.3v output) bold lines indicate high current paths sense + 3 shutdown 3 pgnd3 ndrive 3 v in5 c t5 int v cc5 i th5 sense 5 c t3 + figure 7. ltc1142 layout diagram (see board layout checklist)
16 ltc1142/ltc1142l/ltc1142hv applicatio s i for atio w uu u between pins 1 (15) and 28 (14) should be as close as possible to the ltc1142. 4. does the (+) plate of c in connect to the source of the p-channel mosfet as closely as possible? this ca- pacitor provides the ac current to the p-channel mosfet. 5. is the input decoupling capacitor (1 m f/0.22 m f) con- nected closely between pin 24 (10) and power ground [pin 4 (18) for the ltc1142, pin 5 (19) for the ltc1142- adj]? this capacitor carries the mosfet driver peak currents. 6. are the shutdown pins 2 and 16 for the ltc1142 (pins 3 and 17 for the LTC1142-ADJ) actively pulled to ground during normal operation? both shutdown pins are high impedance and must not be allowed to float. both pins can be driven by the same external signal if needed. 7. for the LTC1142-ADJ adjustable applications, the re- sistive divider r1, r2 must be connected between the (+) plate of c out and signal ground. output crowbar an added feature to using an n-channel mosfet as the synchronous switch is the ability to crowbar the output with the same mosfet. pulling the c t , pin 25 (11) above 1.5v when the output voltage is greater than the desired regulated value will turn on the n-channel mosfet for that regulator section. a fault condition which causes the output voltage to go above a maximum allowable value can be detected by external circuitry. turning on the n-channel mosfet when this fault is detected will cause large currents to flow and blow the system fuse. the n-channel mosfet needs to be sized so it will safely handle this overcurrent condition. the typical delay from pulling the c t pin high and the ndrive pin 6 (20) going high is 250ns. note: under shutdown conditions, the n-chan- nel is held off and pulling the c t pin high will not cause the n-channel mosfet to crowbar the output. a simple n-channel fet can be used as an interface between the overvoltage detect circuitry and the ltc1142 as shown in figure 8. ltc1142 int v cc c t vn2222ll pin 26(12) pin 25(11) from crowbar detect circuit (active when v gate = v in off when v gate = gnd) 1142 f08 figure 8. output crowbar interface troubleshooting hints since efficiency is critical to ltc1142 applications, it is very important to verify that the circuit is functioning correctly in both continuous and burst mode operation. the waveform to monitor is the voltage on the c t , pins 25 and 11. in continuous mode (i load > i burst ) the voltage on the c t pin should be a sawtooth with a 0.9v p-p swing. this voltage should never dip below 2v as shown in figure 9a. when load currents are low (i load < i burst ) burst mode operation occurs. the voltage on the c t pin now falls to ground for periods of time as shown in figure 9b. 3.3v 0v (a) continuous mode operation 3.3v 0v (b) burst mode operation 1142 f09 figure 9. c t waveforms inductor current should also be monitored. look to verify that the peak-to-peak ripple current in continuous mode operation is approximately the same as in burst mode operation. if pin 25 or pin 11 is observed falling to ground at high output currents, it indicates poor decoupling or improper grounding. refer to the board layout checklist. auxiliary windingsCCsuppressing burst mode operation the ltc1142 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. with synchronous switching, auxiliary outputs may be loaded without regard to the primary output load,
17 ltc1142/ltc1142l/ltc1142hv applicatio s i for atio w uu u providing that the loop remains in continuous mode operation. burst mode operation can be suppressed at low output currents with a simple external network which cancels the 25mv minimum current comparator threshold. this tech- nique is also useful for eliminating audible noise from certain types of inductors in high current (i out > 5a) applications when they are lightly loaded. an external offset is put in series with the sense C pin to subtract from the built-in 25mv offset. an example of this technique is shown in figure 10. two 100 w resistors are inserted in series with the sense leads from the sense resistor. r sense 1000pf r2 100 w r1 100 w r3 + c out v out sense + [pin 1(15)] sense [pin 28(14)] 1142 f10 figure 10. suppression of burst mode operation with the addition of r3 a current is generated through r1 causing an offset of: vv r rr offset out = + ? ? ? ? 1 13 if v offset > 25mv, the built-in offset will be cancelled and burst mode operation is prevented from occurring. since v offset is constant, the maximum load current is also decreased by the same offset. thus, to get back to the same i max , the value of the sense resistor must be lower: r mv i sense max ? 75 to prevent noise spikes from erroneously tripping the current comparator, a 1000pf capacitor is needed across pins 1 (15) and pins 28 (14). typical applicatio n s n u 1000pf + + + 1000pf pdrive 1 sense + 1 sense 1 ndrive 1 pgnd1 sgnd1 c t1 i th1 i th2 c t2 sgnd2 pgnd2 ndrive 2 sense 2 v fb2 v fb1 sense + 2 pdrive 2 v in1 shutdown 1 shutdown 2 v in2 ltc1142hv-adj c t2 270pf 5 4 25 27 13 11 18 19 r c2 1k c c1 3300pf c c2 3300pf c t1 270pf r c1 1k 0.22 m f 3 24 17 100pf 100pf 10 9 15 14 16 20 23 1 28 2 6 v out2 5v/2a c out2 220 m f 10v 2 r sense2 0.05 w p-ch si9430dy l2 33 m h d2 mbrs130t3 n-ch si9410dy 0v = normal >1.5v = shutdown 0.22 m f c in2 22 m f 35v 2 c in1 22 m f 35v 2 p-ch si9430dy n-ch si9410dy d1 mbrs130t3 c out1 220 m f 10v 2 l1 25 m h r sense1 0.05 w r2 100k 1% r4 150k 1% r3 49.9k 1% r1 52.3k 1% v out1 3.6v/2a v in 5.2v to 18v r sense1, r sense2 : krl sl-1/2-r050j l1: coiltronics ctx25-4 l2: coiltronics ctx33-5 1142 f11 + figure 11. ltc1142hv-adj dual regulator with 3.6v/2a and 5v/2a outputs
18 ltc1142/ltc1142l/ltc1142hv typical applicatio n s n u figure 12. ltc1142hv-adj high efficiency regulator with 3.3v/2a and 2.5v/1.5a outputs + + + 1000pf pdrive 3 sense + 3 sense 3 ndrive 3 pgnd3 sgnd3 c t3 i th3 i th5 c t5 sgnd5 pgnd5 ndrive 5 sense 5 sense + 5 pdrive 5 v in3 shutdown 3 shutdown 5 v in5 ltc1142hv c t5 150pf 4 3 25 27 13 11 17 18 r c5 1k c c3 3300pf c c5 3300pf c t3 200pf r c3 510 w 0.22 m f 2 24 16 10 9 15 14 20 23 1 28 6 v out5 5v/2a c out5 220 m f 10v 2 r sense5 0.05 w l2 20 m h d2 mbrs130t3 n-ch si9410dy 0v = normal >1.5v = shutdown 0.22 m f c in5 22 m f 25v 2 c in3 22 m f 25v 2 p-ch si9433dy n-ch si9410dy d1 mbrs130t3 c out3 100 m f 10v 3 l1 10 m h r sense3 0.033 w v out3 3.3v/3a v in 5.2v to 8v 1142 f13 + p-ch si9430dy 1000pf r sense3 : krl sl-c1-1/2-r033j r sense5 : krl sl-c1-1/2-r050j l1: coiltronics ctx10-4 l2: coiltronics ctx20-4 figure 13. ltc1142hv high efficiency regulator with 3.3v/3a and 5v/2a outputs 1000pf + + + 1000pf pdrive 1 sense + 1 sense 1 ndrive 1 pgnd1 sgnd1 c t1 i th1 i th2 c t2 sgnd2 pgnd2 ndrive 2 sense 2 v fb2 v fb1 sense + 2 pdrive 2 v in1 shutdown 1 shutdown 2 v in2 ltc1142hv-adj c t2 330pf 5 4 25 27 13 11 18 19 r c2 1k c c1 3300pf c c2 3300pf c t1 330pf r c1 1k 0.22 m f 3 24 17 100pf 100pf 10 9 15 14 16 20 23 1 28 2 6 v out2 3.3v/2a c out2 220 m f 10v 2 r sense2 0.05 w p-ch si9430dy l2 25 m h d2 mbrs130t3 n-ch si9410dy 0v = normal >1.5v = shutdown 0.22 m f c in2 22 m f 35v 2 c in1 22 m f 35v 2 p-ch si9430dy n-ch si9410dy d1 mbrs130t3 c out1 220 m f 10v 2 l1 33 m h r sense1 0.075 w r2 49.9k 1% r4 84.5k 1% r3 51k 1% r1 49.9k 1% v out1 2.5v/1.5a v in 4.5v to 18v r sense1 : krl sl-c1-1/2-1r075j r sense2 : krl sl-c1-1/2-1r050j 1142 f12 + l1: coiltronics ctx33-4 l2: coiltronics ctx25-4
19 ltc1142/ltc1142l/ltc1142hv information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. typical applicatio n s n u figure 15. ltc1142hv-adj high efficiency power supply providing 3.3v/2a with built-in battery charger 1000pf + + + 1000pf pdrive 1 sense + 1 sense 1 ndrive 1 pgnd1 sgnd1 c t1 i th1 i th2 c t2 sgnd2 pgnd2 ndrive 2 sense 2 v fb2 v fb1 sense + 2 pdrive 2 v in1 shutdown 1 shutdown 2 v in2 ltc1142hv-adj c t2 330pf 5 4 25 27 13 11 18 19 r c2 1k r x 51 w c c1 3300pf c c2 3300pf c t1 200pf r c1 1k 0.22 m f 3 24 17 100pf 100pf 10 9 15 14 16 20 23 1 28 2 6 v out2 3.3v/2a v batt 4 cells nicad c out2 220 m f 10v 2 r sense2 0.05 w p-ch si9433dy l2 25 m h d2 mbrs140t3 n-ch si9410dy 0.22 m f c in2 22 m f 25v 2 c in1 22 m f 35v 2 p-ch si9430dy n-ch si9410dy d1 mbrs140t3 d3 mbrs340t3 c out1 220 m f 10v l1 50 m h r sense1 0.1 w r2 274k 1% r4 84.5k 1% r3 51k 1% r1 49.9k 1% v in 8v to 18v from wall adapter 0v = charge on >1.5v = charge off 0v = output on >1.5v = 3.3v output off r sense1 : krl sl-c1-1/2-1r100j r sense2 : krl sl-c1-1/2-1r050j l1: coiltronics ctx50-4 l2: coiltronics ctx25-4 fast charge = 130mv/r sense1 = 1.3a trickle charge = 130mv/r sense1 = 100ma 1142 f15 + ??for trickle charge vn2222ll figure 14. ltc1142 triple output regulator with switched 12v output + + + 1000pf pdrive 3 sense + 3 sense 3 ndrive 3 pgnd3 sgnd3 c t3 i th3 i th5 c t5 sgnd5 pgnd5 ndrive 5 sense 5 sense + 5 pdrive 5 v in3 shutdown 3 shutdown 5 v in5 ltc1142 c t5 200pf 4 3 25 27 13 11 17 18 r c5 510 w c c3 3300pf c c5 3300pf c t3 390pf r c3 510 w 1 m f 2 24 16 10 9 15 14 20 23 1 28 6 v out5 5v/2a 220 m f 10v 2 c9 22 m f 35v r sense5 0.04 w 30 m h d2 mbrs140t3 0v = normal >1.5v = shutdown 1 m f 22 m f 25v 2 22 m f 25v 2 v in 6.5v to 14v n-ch si9410dy n-ch si9410dy d1 mbrs140t3 100 m f 10v 2 l1 33 m h r sense3 0.05 w v out3 3.3v/2a 1142 f14 + + p-ch si9430dy p-ch si9430dy 0.01 m f r sense3 : krl sl-c1-1/2-0r050j r sense5 : krl sl-c1-1/2-0r040j l1: coiltronics ctx33-4 t1: dale lpe-6562-a026 primary: secondary = 1:1.8 22 w r1 100 w t1 12v enable 0v = 12v off >3v = 12v on (6v max) 1000pf d3 mbrs140t3 r3 649k 1% r4 294k 1% 20pf + 22 m f 25v 12v/150ma lt1121 v out shutdown v in adj 100 w vn2222ll r5 18k + gnd 5 8 3 2 1 +
20 ltc1142/ltc1142l/ltc1142hv linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 ? linear technology corporation 1995 lt/gp 1196 5k rev c ? printed in usa typical applicatio n s n u set resistance (k w ) 0 1400 1200 1000 800 600 400 200 0 3 1142 f16 12 4 output current (ma) figure 16. ltc1142hv-adj output current vs trickle charge set resistance (r x ) for the circuit in figure 15 using a 0.1 w current sense resistor r sense1 note: for additional high efficiency circuits, see application note 54. dimensions in inches (millimeters) unless otherwise noted. package descriptio u related parts part number description comments ltc1143 dual step-down switching regulator controller dual version of ltc1147 ltc1147 step-down switching regulator controller nonsynchronous, 8-pin, v in 16v ltc1148 step-down switching regulator controller synchronous, v in 20v ltc1149 step-down switching regulator controller synchronous, v in 48v, for standard threshold fets ltc1159 step-down switching regulator controller synchronous, v in 40v, for logic level fets ltc1174 step-down switching regulator with internal 0.5a switch v in 18.5v, comparator/low battery detector ltc1265 step-down switching regulator with internal 1.2a switch v in 13v, comparator/low battery detector ltc1266 step-up/down switching regulator controller synchronous n- or p-channel fets, comparator/low battery detector ltc1267 dual high efficiency synchronous switching regulator v in to 40v ltc1574 step-down switching regulator with internal 0.5a switch v in 18.5v, comparator and schottky diode g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **

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